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Features
* Compliant with Trusted Computing Group (TCG) Trusted Platform Module (TPM) Main * * * * * * * * * * * *
Specification Version 1.2 Compliant with TCG PC Client Specific TPM Interface Specification Version 1.2 Single Chip Turnkey Solution Hardware Asymmetric Crypto Engine 2048 RSA Sign in 500 ms AVR(R) RISC Microprocessor 33 MHz LPC (Low Pin Count) Bus for Easy PC Interface Secure Hardware and Firmware Design True Random Number Generator (RNG) - FIPS 140.2 compliant Secure Real-time Clock Option 3.3V 10% Supply Voltage 28-lead TSSOP Package or 40-lead QFN Package 0-70C Temperature Range
Trusted Platform Module AT97SC3203
Summary
Description
The AT97SC3203 Trusted Platform Module (TPM) is the latest offering from Atmel, the world's leading choice for TPMs. Atmel, supplier of the world's first production v1.1b TPM, the AT97SC3201, expands its success into v1.2 TPMs with the AT97SC3203. Atmel continues to pace the development of TPM technology and actively participates in the Trusted Computing Group (TCG) and contributes expertise in the development of the TPM specifications. By utilizing Atmel TPMs, you can be confident that you are implementing the most advanced TPMs available on the market today and in the future. The AT97SC3203 is a fully integrated security module designed to be integrated into personal computers and other embedded systems. It implements version 1.2 of the Trusted Computing Group specification for Trusted Platform Modules. The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA signature in 500 ms and a 1024-bit RSA signature in 100 ms. Performance of the SHA-1 accelerator is L50 s per 64-byte block. In most cases, TCG key generation operations will be completed using a proprietary mechanism in less than 1 msec. The chip communicates with the PC through the LPC interface. The TPM supports SIRQ (for interrupts) and CLKRUN to permit clock stopping for power savings in mobile computers.
Advance Information
Rev. 5116AS-TPM-7/05
Note: This is a summary document. A complete document is available under NDA. For more information, please contact your local Atmel sales office.
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Figure 1. AT97SC3203 Block Diagram
ROM Program
EEPROM Program
33 MHz LPC Interface
AVR(R) 8/16 Bit CPU
SRAM
EEPROM Data
GPIO6
VBB 32.768 kHz
GPIO RNG RTC Timer Physical Security Circuitry CRYPTO Engine
Figure 2. Atmel AT97SC3203 TPM Pin Configuration
28 pin TSSOP 9.6 mm, 0.65 mm pitch 6.1 mm plastic width 40 pin QFN 6.0 mm x 6.0 mm 0.50 mm pitch NC NC NC NC NC NC NC NC LPCPD# SERIRQ 40 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 NC XTALI/32K in XTALO NC NC NC NC NC CLKRUN# LRESET# NC GND SB3V GPIO6 NC TestI TestBI/BADD 3V GND VBAT 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 LAD0 GND 3V LAD1 LFRAME# LCLK LAD2 3V GND LAD3
NC 1 NC 2 NC 3 GND 4 SB3V 5 GPIO6 6 NC 7 TestI 8 TestBI/BADD 9 3V 10 GND 11 VBAT 12 XtalI/32K in 13 XtalO 14
28 LPCPD# 27 SERIRQ 26 LAD0 25 GND 24 3V 23 LAD1 22 LFRAME# 21 LCLK 20 LAD2 19 3V 18 GND 17 LAD3 16 LRESET# 15 CLKRUN
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5116AS-TPM-7/05
AT97SC3203
Table 1. Pin Descriptions
Name LAD[3:0] LFRAME# LPCPD# TSSOP Pin # 17, 20, 23, 26 22 28 QFN Pin # 30, 27, 24, 21 26 32 Type Input or Output Input Input Input or Output Input Input Description LPC Multiplexed Command, Address, Data: Internal pull-ups are provided. LPC frame: Indicates the start of an LPC cycle, or an abort. Power Down: Indicates that the TPM should prepare for power to be shut off on the LPC interface. If this pin is unused, it should be tied to the 3V power supply pin through a resistor. PCI Clock Run: Active low output enabling the system LPC clock. If this pin is unused, it should be tied to ground. 33MHz PCI clock provides timing for all transactions on the PCI bus. PCI signal to reset all devices that reside on the PCI bus. Serialized Interrupt Request Signal. If the SERIRQ function is enabled, this pin should be connected to the CPU SERIRQ input, and the line pulled to the 3V power supply pin through a resistor. If this pin is unused, it should be tied to the 3V power supply pin through a resistor. Standby 3.3V Supply. If no separate standby power supply is connected to this pin, the pin should be tied directly to the 3V power supply pin. Primary 3.3V DC power supply input rail supplied by the motherboard. May be referred to as Vcc. System ground. No connect. This pin may be floated. If the XOR chain I/O test mode is used, the pin should be tied to ground directly or through a resistor. Reserved for the SMBus Data I/O function. No connect. This pin may be floated. If the XOR chain I/O test mode is used, the pin should be tied to ground directly or through a resistor. Reserved for the SMBus Clock Input function. Vendor No Connect, as designated in the PC Client TIS specification. This pin may be floated. If the XOR chain I/O test mode is used, the pin should be tied to ground directly or through a resistor. General Purpose Input/Output. Internal Pull-up Resistor. This pin is mapped to NV Index TPM_NV_INDEX_GPIO_00 and serves as the GPIO-Express-00. Default TPM configuration: GPIO Input. GPIO6 also serves as the XOR chain Output during I/O test mode. No Connect. This input pin has an internal pull-down resistor and may be floated. If the XOR chain I/O test mode is used, the pin should be tied to the 3V power supply directly or through a resistor. TPM manufacturing test input disabled. This pin may be floated. If the XOR chain I/O test mode is used, the pin should be tied directly to ground. TestBI and BADD functions disabled. This pin should be tied directly to ground.
CLKRUN# LCLK LRESET#
15 21 16
19 25 20
SERIRQ
27
31
Input or Output
SB3V
5
3
Input
3V GND NC
10, 19, 24 4, 11, 18, 25 1
8, 23, 28 2, 9, 22, 29 39
Input Input Output
NC
2
40
Output
VNC
3
1
Output
GPIO6
6
4
Input or Output
NC
7
5
Input
TestI
8
6
Output
TestBI/BADD
9
7
Input
3
5116AS-TPM-7/05
Table 1. Pin Descriptions (Continued)
Name VBAT XtalI/32K in XtalO TSSOP Pin # 12 13 14 QFN Pin # 10 12 13 Type Input Input Output Description 3.3V Battery Input. If no external battery is connected to this pin, the pin should be tied directly to the 3V power supply pin. 32 kHz Crystal Oscillator Input or 32 kHz Clock Input. This pin should be tied to ground if not used. 32 kHz Crystal Oscillator Output.
Absolute Maximum Ratings (Preliminary)
Operating Temperature..............................0C to +70C Storage Temperature (without Bias)...........0C to + 70C Voltage on I/O Pins..............................-0.1 to VCC +0.3V Voltage on VCC with Respect to Ground.................6.0V Maximum ESD Voltage..........................................2000V
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification may cause temporary or permanent failure. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 2. DC Parameters (Preliminary) VCC = 3.0 to 3.6V; Temperature = 0 to 70C
Symbol Vcc Icc IST ISL IBB ILIO VIH VIL VOH VOL IOLCR CI Notes: Parameter Supply Voltage Operating Current at fclk = 33 MHz Static Current Sleep Current, Chip Idle Battery Current Input Leakage Input High Threshold Input Low Threshold Output High Voltage Output Low Voltage Output Low Current, CLKRUN# Input Pin Capacitance 1. These parameters guaranteed by design. 7 6 0.5 * Vcc -0.5 0.9 * Vcc 0.98 * Vcc 0.1 * Vcc Min 3.0 Nom 3.3 25 5 40 2 0.1 Max 3.6 50 10 100 4 3 0.5 + Vcc 0.3 * Vcc Units V mA mA A A A V V V V mA pF At IOUT = -500 A V At IOUT = 1.5 mA At VOUT = .615 * VCC Note 1 Vcc =3.6V; fxtal = 0 Hz; active inputs VCC = 3.6V; fxtal = 0 Hz VCC = 0V; fxtal = 0 Hz Vin = VCC or GND Notes
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AT97SC3203
Table 3. AC Parameters Cl = 10pf.; VCC = 3.0 to 3.7V; Temperature = 0 to 70-C
Symbol TVAL TON TOFF TSU TH TRST TRSTCLK TRSTOFF TCLKIN TCLKL O TCLKHI Notes: Parameter CLK to Signal Valid Delay - LAD0-3 Float to Active Delay Active to Float Delay Input Setup Time to CLK Input Hold Time from CLK Reset Active Time After Power Stable Reset Active After CLK Stable Reset Active to Output Float Delay CLK Period CLK Low Duration CLK High Duration 29.5 13.4 13.4 30 7 0 1 100 40 31 18 18 2 -500 Min 2 2 Nom 5 4 28 Max 11 Units nS nS nS nS nS mS mS nS nS nS nS Note 1 Note 1 Note 1 Note 3 Note 2, Note 3 Note 2, Note 3 Notes Measured at Vtrise = 0.285 * VCC and Vtfal = 0.615 * VCC. Measured from clk at Vtest = 0.4* VCC; Load = 200.
1. These parameters guaranteed by design. 2. All parameters measured with respect to signal crossing Vtest = 0.4 * VCC unless otherwise noted. 3. The minimum parameter must never be violated under any circumstances unless Lreset# is asserted. If proper CLKRUN# signaling is observed, the maximum specification can be violated.
Table 4. Ordering Information
Ordering Code(1) AT97SC3203-01AC AT97SC3203-X1AC AT97SC3203-01MC AT97SC3203-X1MC Notes: Package 28A3 (TSSOP) 28A3 (TSSOP) 40ML1 (QFN) 40ML1 (QFN) Lead-free
(2)
Operation Range Commercial (0 to 70 C) Lead-free
(2)
Commercial (0 to 70 C) Commercial (0 to 70 C) Commercial (0 to 70 C)
1. Current as of publication date. Contact Atmel marketing for status update. 2. Also RoHS
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5116AS-TPM-7/05
Package Drawing
28A3 - TSSOP
b
L L1 E E1
e
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm)
A
D
A2
SYMBOL D E E1
MIN 9.60
NOM 9.70 8.10 BSC
MAX 9.80
NOTE 2, 5
6.00 - 0.80 0.19
6.10 - 1.00 - 0.65 BSC
6.20 1.20 1.05 0.30
3, 5
Side View
A A2 b e L L1
4
0.45
0.60 1.00 REF
0.75
Notes:
1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 1/8/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch, Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 28A3
REV. A
6
AT97SC3203
5116AS-TPM-7/05
AT97SC3203
40ML1 - QFN
A D N A2 A3 1 2 3 E
Pin 1 Indicator
A1
Top View
L 0
Side View
D2
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM 6.00 BSC 6.00 BSC 3.95 3.95 0.0 4.10 4.10 0.85 0.01 0.65 0.20 REF 0.30 0.40 0.50 BSC 0.18 0.23 0.30 2 0.50 4.25 4.25 0.90 0.05 0.70 MAX NOTE
E2 1 2 3 b
D E D2 E2 A A1 A2
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area.
R
TITLE 2325 Orchard Parkway 40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad San Jose, CA 95131 Flat No Lead Package (MLF2)
5116AS-TPM-7/05
N e PIN1 ID
A3 L e b
Bottom View
3/9/04 DRAWING NO. 40ML1 REV. A
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5116AS-TPM-7/05

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